Fpga jobs

I’m looking for an experienced FPGA engineer to create a one-off firmware build for an Artix-7–based LeetDMA/Screamer PCIe DMA card. The goal is to make the card appear on the bus exactly like my reference network interface card so automated heuristic checks see no difference. Scope of work • Re-order and modify the Capability Pointer chain inside so the PCIe config space layout mirrors the donor NIC byte-for-byte. • Implement full TLP transaction handling, including correct completion timing and status codes. • Provide accurate BAR sizing and address decoding as the original NIC does. • Add proper MSI / MSI-X interrupt setup with working vectors and masking logic. Context and constraints This firmware is for security research, not prod...

I need a fresh Quartus build of the open-source USRP1 FPGA code at I have added a roughly 100-line Verilog patch generated by AI for minor adjustments to improve performance. So, a compiled version has not been tested, but the unpatched version works well. The first step is simply getting the design through synthesis, place-and-route, and generating a working bitstream for the Cyclone target used by the USRP1 board. No functional re-work or optimisation is required; I just want the patched design to compile cleanly with the standard settings already in the repository. You will therefore need a working installation of Intel/Altera Quartus (the version known to build this project is ideal) plus any supporting IP files the project expects. Please

...Semiconductor Internship Opportunities I am a Electrical Engineering student at Thapar Institute of Engineering & Technology, currently looking for an **internship in Hardware, Semiconductor, VLSI, Electronics, Embedded Systems, PCB Design, or Validation** in **Bangalore, Gurgaon, or remotely**. I have hands-on experience in: * PCB Design (Altium Designer) * Embedded Systems & Microcontrollers * FPGA / Digital Electronics * Hardware Testing & Validation * VLSI / Semiconductor fundamentals * Robotics and electronics projects I am looking for someone who can **help identify suitable internship openings, connect me with relevant companies/recruiters, or assist with getting my profile considered**. **Preferred locations:** Bangalore / Gurgaon **Duration:** 6 months ...

...filters; * digital filters; * DSP; * or a combination of these methods. The selected implementation shall be documented. --- ## 6. AFSK/FSK DEMODULATION The module shall reliably distinguish: **MARK = 2083.3 Hz** and **SPACE = 1562.5 Hz** at approximately: **520.83 bit/s** The demodulation method may use a PLL, frequency discriminator, Goertzel algorithm, DSP, MCU, dedicated modem IC, FPGA, or another technically justified method. The demodulator shall provide a digital output representing the recovered MARK/SPACE data. --- ## 7. DIGITAL OUTPUT AND MCU INTERFACE The primary output shall be: **DATA_OUT** Preferred electrical level: **3.3 V logic** The output shall preserve sufficient timing and data integrity for an external MCU to subsequently perform: **DATA_O...

HLS / FPGA Developer – Low-Latency Algorithmic Trading We are looking for an experienced HLS / FPGA Developer to join our team and work on the development and hardware acceleration of high-performance stock trading strategies. The ideal candidate should have strong hands-on experience in FPGA architecture, RTL design, HLS, high-speed interfaces, and low-latency data processing, with an interest in applying these skills to algorithmic trading. Key Responsibilities • Develop and optimize low-latency trading strategies and market-data processing pipelines on FPGA. • Translate trading algorithms into efficient RTL/HLS implementations. • Design and optimize FPGA architectures for ultra-low-latency and deterministic execution. • Develo...

I’m building an industrial control system that brings an ARM Cortex-M microcontroller together with a Xilinx FPGA and a companion DSP on a compact, high-reliability multilayer board. The design calls for careful layer stack-up, controlled-impedance routing for high-speed buses between the MCU, FPGA and memory, as well as robust isolation and filtering for noisy factory environments. I already have a block diagram and rough pin assignments; what I need now is a complete hardware package that takes the concept all the way to production-ready files. — 6- to 10-layer schematic and PCB layout, including power architecture, differential pairs and test-point strategy — Verified design rules for 4 mil traces / 8 mil vias (or tighter if you can justify it) &mda...

I need new DMA firmware developed for an FPGA. Requirements: - Expertise in FPGA development - Experience with DMA and firmware design - Proficiency in relevant programming languages (like VHDL or Verilog) Ideal Skills: - FPGA architecture knowledge - Strong debugging and problem-solving skills - Previous DMA firmware projects experience No strict deadline for completion. Looking for quality work.

...and turning it into a rugged, handheld instrument that works reliably on Platinum, Silver, Nickel, and brass samples. The core tasks include designing the full analog front-end (pulser/receiver, low-noise pre-amp, gain control, anti-alias filters), selecting and driving the piezo transducers, and implementing a precise time-of-flight algorithm in an embedded platform. I am open to ARM, DSP, or FPGA solutions as long as we can achieve micro-second timing resolution and keep power draw low enough for a battery-powered unit. On the digital side I will need firmware that triggers the pulse, captures echoes through a high-speed ADC, processes the signal (envelope detection, filtering, thresholding), and converts flight time to velocity with temperature compensation. A simple menu-...

I am working ...of Exanic-based pipelines—whether through driver parameters, FPGA firmware tweaks, user-space memory mapping, or smarter batching in the exasock code path—I would like your help. What I can provide • Source snippets and current build flags • Access to a staging server equipped with the same NIC and an OLTP test harness • Benchmarks collected with hardware time-stamps for every stage above What I need in return • A tuned configuration or code patch set that demonstrably lowers latency (before/after numbers captured with the card’s on-board clock) • A short write-up of the adjustments so I can reproduce the result in production If you have a proven track record lowering packet-send latency on Exanic or similar...

Job Description: VLSI Design Trainer / Technical Instructor About the Role We are looking for an experienced VLSI Design Trainer from Vietnam to men...years in VLSI physical design, RTL design, or verification Industry background Worked in semiconductor / EDA / chip design company preferred Teaching experience Prior training or mentoring experience is a strong plus Tools familiarity OpenROAD + Yosys (mandatory); Cadence/Synopsys (preferred) Good to Have (Bonus Skills) • Experience with Efabless / Google Open MPW shuttle tapeout • Familiarity with FPGA flows (Vivado / Quartus) • Knowledge of low-power design techniques (multi-Vt, clock gating, power gating) • Exposure to formal verification tools (SymbiYosys, JasperGold) • Prior experience handling batch size...

...high-accuracy data conversion. The job is to design the entire ADC/DAC front-end, marrying the sensitive analog path with the supporting digital logic so the output is ready to drop straight onto my main PCB. What I need from you • A complete schematic showing the analog input stage, the chosen ADC and DAC devices, reference circuitry, clocking, and the glue logic that links everything to an MCU or FPGA header. • Component selection with justification, balancing performance, availability, and cost. • Simulations that verify noise, linearity, and timing (SPICE, LTspice, or similar). • A clean, well-annotated PCB layout file (Altium, KiCad, or Eagle—your choice, just tell me up front) plus Gerbers ready for fabrication. • A BOM with manufac...

I'm seeking a skilled developer to create fully emulated firmware for a DMA card. The firmware must be compatible with Windows and able to emulate certain functionalities, specifically: - Network protocols - Peripheral device interactions Additionally, the firmware should support and be compatible with various anti-cheat systems, including: 1 EAC (Easy Anti-Cheat) 2 BE (BattlEye) 3 FACEIT Anti-Cheat (Highest level of Anti Cheat, presently) With Full BAR support For this project I am assuming you possess experience in firmware development, a deep understanding of DMA card functionalities, and familiarity with the specified anti-cheat systems.

...`` plus the known current state (PowerCell1 routed, open blockers). For exact numbers, see the MCP option at the end. ## Status by phase (effort-weighted) | Phase | Session | Budget (h) | Est. done | Remaining | |---|---|---|---|---| | Hierarchical schematic | 1 | 2-3 | ✅ ~100% | — | | Power Input | 2 | 1-2 | ✅ ~100% | — | | PowerCell sheet | 3 | 2-3 | ✅ ~95% | (topology verification) | | FPGA Core | 4 | 3-4 | ⚠️ ~30% | U402 real pinout/symbol | | MCU Core | 5 | 1-2 | ⚠️ ~50% | U501 full-pin symbol | | ADC + others | 6 | 2 | ⚠️ ~50% | U601/U602 symbols | | ERC + Annotation | 7 | 1 | ⚠️ ~40% | PWR_GOOD error, J702/J703 short | | Footprint assignment | 8 | 1-2 | ✅ ~90% | — | | Netlist + open PCB | 9 | 0.5 | ✅ 100% | — | | **PCB Layout** | 10 | **16-24** | ...

I am working on a Zynq-based project and need the programmable logic side coded to handle the embedded system control tasks that my ARM cores alone cannot meet. The goal is to off-load time-critical control loops and deterministic signal routing into the FPGA fabric so the whole design stays responsive under load. You can use Xilinx Vivado (and Vitis if you prefer to wrap software hooks) as the toolchain. I will provide the current block diagram, timing requirements, and my existing software drivers; you return synthesizable HDL, a brief test-bench that shows the control logic reacting to inputs, and the bitstream I can drop straight into my project. Clear documentation of I/O pin assignments and register maps will make integration painless. If you have already built control logic...

Create zynq FPGA carrier board based from alinx SOM. I make the deadline long because it will include design supporr

...government or enterprise buyers. The list should include contact details, company fit, strategic relevance, and suggested approach. 3. Technical feasibility review Review the SDNS concept from a hardware and networking perspective, including FPGA prototyping, ASIC feasibility, optical transceiver integration, deterministic low-latency routing, secure network-card design, and potential deployment inside AI data center environments. 4. Prototype and engineering roadmap Prepare a practical roadmap for moving from concept to prototype: PCB design, FPGA implementation, optical I/O integration, firmware/security logic, lab testing, latency benchmarking, and later ASIC migration if technically justified. 5. Outreach and introduction strategy Create professional outreach messag...

For a Spanish speaker in Barcelona! I am bringing together a compact laser platform and an FPGA-based control board here in Barcelona, and I need an engineer who can sit beside the hardware, plug in the scopes and power rails, and push the overall performance to its limit. The work is squarely at the crossroads of optics and digital electronics: you will be aligning the laser path with a set of optical sensors, tightening the signal chain that feeds the onboard FPGA signal processors, and making sure the power supplies deliver exactly what the photonics and the logic fabric demand—no more, no less. What I expect you to drive: • Physical and electrical integration of the laser module with the FPGA board • Low-noise routing between optical sensors ...

Hi I will share the details with the shortlisted candidates. Thanks

...layout but without traces connecting them, also some parts are not correct in PCB, specifically the FPGA has to be changed to another model/part. I would like to have also the complete pcb layout generated but I want to keep the cost for now really low so I can accept just the schematic work. If someone though wants to bid for both schematic and layout then I could consider if the bid suits my budget. Either way as a next stage it will be another project that will cover schematic changes, PCB generation (or finalization if someone did it already), BOM generation and all actions to be ready for manufacture. Please specify in your bid if it is for schematic only or for layout too. The schematic has FPGA/ADC/DAC/CODEC/CLOCK/POWER/etc spread in 12 pages now in .pdf and it shou...

Overview This document specifies the requirements for a GPS L1 C/A signal tracking engine implemented in VHDL on a Xilinx Zynq-7000 FPGA. The tracking engine receives pre-recorded baseband I/Q samples from a Pocket SDR front-end (MAX2771 in zero-IF mode), streamed from a host PC through the Zynq PS into the PL via AXI DMA. It performs carrier tracking (Costas loop), code tracking (delay lock loop), and correlation to produce the measurements needed for position computation. The PC captures sample data and performs acquisition. The Zynq PS relays data and configuration to the PL, which handles the tracking. The PL outputs are then read by the PS, sent back to the PC via ETH, and verified against a Python tracking implementation. Xilinx vendor IP cores may be used where they simplify...

Description: Creation of the initial written documentation describing the proposed debugging workflow, recommended setup sequence, and safety considerations for working with the DSP/FPGA platform. Deliverable: Written setup/documentation guide with recommended workflow notes Acceptance Criteria: Client receives the written documentation package in readable digital format.

I need an FPGA implementation for optimizing the Ising model using simulated annealing. The goal is to obtain the energy state configuration. Key Requirements: - FPGA programming expertise - Proficiency in simulated annealing - Strong background in Ising model and optimization techniques Deliverables: - Optimized energy state configuration - Documentation of the implementation process Ideal Skills: - FPGA design and development - Algorithm optimization - Experience with simulated annealing

I need an FPGA developer to complete an existing SPI slave system on an iCE40 4k HX. The RTL is mostly written and passes individual testbenches. The work is integration, cleanup, adding ECC/CRC, synthesis, and hardware testing. **What exists:** - SPI Mode 0 slave command processor (Verilog) - Downstream IP with dual-port BRAM and status registers - PWM logic-word consumer (VAK_SSE) - Individual module testbenches (Icarus Verilog) **What needs to be done:** 1. Design review — document the current system, identify all issues 2. Bug fixes — resolve known issues, clean up code 3. Add parameterized ECC (Hamming/Hsiao for 16/24/32-bit words) and CRCn (11/18/26-bit) 4. Write an integration testbench covering the full path (SPI → BRAM → PWM) 5. Synthesize for iCE40 ...

...spreadsheet of qualified startup leads, including decision-maker contact details, short project context and confirmation they are open to an intro call • Weekly progress summary highlighting outreach channels used and response rates • Warm introduction or meeting scheduled for every accepted lead Acceptance criteria • Leads must be genuine startups (seed to Series C) developing ASIC, SoC or FPGA products • Each lead expresses a current functional verification pain point and interest in external support • Contact information is current, direct and non-generic If you have a proven track record generating leads for technical services or selling into the semiconductor design space, let’s talk about timelines and how many introductions yo...

...parameterisable depth, and a simple hazard-free write-back mechanism • Instruction Decoder that converts the Alpha binary format into the internal control signal set expected by the software controller Multiplexer and control unit I’m happy for you to implement the blocks in Verilog, VHDL, or SystemVerilog—choose whichever fits your workflow—as long as the modules synthesize cleanly in a mainstream FPGA toolchain and come with a self-checking testbench. Deliverables will be: 1. Source code for each module, clearly commented 2. A top-level wrapper that shows how the software control path interacts with the datapath signals 3. Testbenches (plus scripts) that demonstrate correct operation over a representative instruction mix 4. A brief README expla...

Project Goal We are looking for an experienced FPGA/SoC engineer to guide and mentor a university-level engineering project focused on developing a reusable SoC/FPGA validation framework for controller IP cores generated from MATLAB/Simulink using HDL Workflow Advisor. The initial case study is a PID controller implemented on a Xilinx SoC FPGA platform using MATLAB/Simulink, HDL Coder, and Vivado. Scope of Work The freelancer will guide the student in: • Designing and validating controller algorithms in MATLAB/Simulink • Generating HDL and packaging custom IP cores using HDL Workflow Advisor • Creating a custom Vivado reference design instead of using the default HDL Workflow Advisor design • Integrating the controller IP with: * Zynq Processi...

Conference paper in IEEE format for the topic FPGA implementation of Music Algorithm for DOA estimation. I have completed the project and have results

FPGA-Based Real-Time Laser Plasma Volumetric Display Controller Overview: I'm building a volumetric holographic display system using laser-excited plasma. The core challenge is a real-time FPGA controller that synchronizes laser pulses, galvanometer mirrors, and sensor feedback with sub-10 microsecond latency. Think Tony Stark holograms — that's the end goal. What I need built: A Verilog module that controls laser pulse timing, reads x/y/z sensor coordinates, calculates next plasma position, and drives galvo mirror signals — all within a tight real-time feedback loop. Simulation in Xilinx Vivado first, then synthesis onto FPGA hardware. You need to know: Verilog / VHDL FPGA development (Xilinx preferred) Real-time control systems Basic un...

FPGA-Based Real-Time Laser Plasma Volumetric Display Controller Overview: I'm building a volumetric holographic display system using laser-excited plasma. The core challenge is a real-time FPGA controller that synchronizes laser pulses, galvanometer mirrors, and sensor feedback with sub-10 microsecond latency. Think Tony Stark holograms — that's the end goal. What I need built: A Verilog module that controls laser pulse timing, reads x/y/z sensor coordinates, calculates next plasma position, and drives galvo mirror signals — all within a tight real-time feedback loop. Simulation in Xilinx Vivado first, then synthesis onto FPGA hardware. You need to know: Verilog / VHDL FPGA development (Xilinx preferred) Real-time control systems Basic un...

I’m working on an FPGA-based power-electronics design that performs direct AC-to-AC conversion, and I’d like an experienced set of eyes on the project. Rather than a full redesign, I need targeted, practical suggestions that will help refine the existing architecture, tighten the control loops, and ensure the hardware description (VHDL/Verilog) and gate-level timing are truly aligned with the switching requirements of high-frequency power conversion. Here’s what I’m looking for: • A concise design review of the current top-level schematic, clocking scheme, and PWM generation logic. • Specific, actionable recommendations for improving efficiency, reducing switching losses, and safeguarding against common AC-to-AC pitfalls such as commutation ov...

...board integrating: * Multi-rail power management * Digital control system * High-voltage generation architecture (conceptual + control side) * Touchscreen UI interface * Precision timing and current control For HV use different board DIODE & Capacitor multiplier until 100 KV stages The system will be controlled via a microcontroller (STM32H743VIT6 + ADC eksternal ADS127L11 / AD7768 / ADS131M08 or FPGA ARTIX 7, there is analog from Photo Multiplier Tube , amplified with low noise and then to noise pass filter then integer before to high speed adc minimum 16 bit ) and all graphic connected to a Windows 11-based mini computer for UI processing. Your task only give rawa output from microcontroller related voltage, current and exposure time precision. Otherwise windows software...

Our existing design was written ...builds under Vivado, and I can provide constraint files, limited board documentation, and schematics for the new module. You will analyse the differences, update pin-outs, clocks, memory interfaces, and any IP parameters affected by the hardware change, then verify the design through simulation and an on-board test build. Deliverables • Updated project repository compiling for the new ENCLUSTRA FPGA • Revised constraint files and any modified HDL or IP configuration • A brief migration report describing what changed, why, and how to reproduce the build When you send your proposal, please outline your migration plan, tool versions you intend to use, estimated milestones, and any prior work that proves you have handled sim...

This task is for generating a KiCad v10.0 schematic from a given PDF. And if someone wants to also generate the pcb layout for it is welcome but the budget is very tight. There is an unfinished KiCad project that has the...pcb layout but without traces connecting them. I would like to have also the complete pcb layout generated but I want to keep the cost for now really low so I can accept just the schematic work. If someone though wants to bid for both schematic and layout then I could consider if the bid suits my budget. Please specify in your bid if it is for schematic only or for layout too. The schematic has FPGA/ADC/DAC/CODEC/CLOCK/POWER/etc spread in 12 pages, whoever wants to see more information so to bid, just ask and I'll direct you to the unfinished project and the...

I need an engineer who can take my functional requirements and turn them into clean, synthesizable SystemVerilog that runs on the DE-10 FPGA kit. The work covers the full RTL flow—coding the logic, building self-checking test-benches, running ModelSim simulations, and closing on timing before hand-off. You are free to follow your own coding style so long as the code is readable, well-commented, and synthesizes without warnings. The critical point is that every module is fully verified: all corner cases exercised, assertions in place, coverage collected, and a concise report delivered alongside waveform evidence. I’m based in Ho Chi Minh City and would strongly prefer someone who can meet on-site when needed to review schematics, probe the board, and iterate quickly...

I’m refining a set of custom boards that combine an FPGA-based signal generator with several ESP32 modules. The immediate gap is in analog and digital circuit design: I need a fresh set of eyes to review, debug, and improve the front-end and conditioning stages so our multi-channel waveforms stay clean from kHz up into the low-MHz range. You will also find yourself touching the programmable logic; I use both VHDL and Verilog, so fluency in either (or ideally both) is welcome when tweaks to the signal-generation core are required. On the microcontroller side each ESP32 handles data processing, manages communication protocols, and drives attached peripherals, all written in C/C++. Expect to dive into that firmware whenever hardware changes ripple upward. Key objectives &...

...PCIe endpoint (e.g., a Wi-Fi adapter). The card provides transparent passthrough of the endpoint device to the host system, while embedding an FPGA-based DMA engine capable of bus mastering, memory injection, and packet manipulation. Control of the DMA engine is performed via the PCILeech software suite, enabling flexible direct memory access operations. Functional Blocks 1. PCIe Passthrough Bridge • Provides a transparent PCIe x1 interconnect between the host computer and the attached endpoint device. • Maintains compliance with the PCIe protocol to ensure the endpoint is enumerated by the host as if connected directly. 2. FPGA Subsystem (AMD/Xilinx FPGA) • Implements custom PCIe cores for bus mastering and DMA transfers. • Supports injection of...

...PCIe endpoint (e.g., a Wi-Fi adapter). The card provides transparent passthrough of the endpoint device to the host system, while embedding an FPGA-based DMA engine capable of bus mastering, memory injection, and packet manipulation. Control of the DMA engine is performed via the PCILeech software suite, enabling flexible direct memory access operations. Functional Blocks 1. PCIe Passthrough Bridge • Provides a transparent PCIe x1 interconnect between the host computer and the attached endpoint device. • Maintains compliance with the PCIe protocol to ensure the endpoint is enumerated by the host as if connected directly. 2. FPGA Subsystem (AMD/Xilinx FPGA) • Implements custom PCIe cores for bus mastering and DMA transfers. • Supports injection of...

I have a completed research manuscript in the field of post-quantum cryptography's (PQC) hardware-software co-design on FPGA. The research, methodology, data, and results are fully complete. I need a professional academic writer/editor to rewrite the entire manuscript text while preserving the original technical meaning, then ensure it passes AI detection and plagiarism checks. I will provide **text only with references**—no figures, tables, algorithms, or equations. These elements are finalized separately and do not need editing. I am ready to supply the current manuscript (around 11,000 words plus references) and can answer field-specific questions quickly to keep the turnaround smooth. Scope of Work 1. Full Manuscript Rewriting & Academic Language Editing Rewrit...

...complete M.Tech-level project in the domain of Embedded Systems — from concept to implementation to documentation — that is also suitable for publication in a reputed conference. Scope of Work: The selected freelancer will be responsible for the following: 1. Project Development Propose a novel or improved project idea in the Embedded Systems domain (e.g., IoT-based systems, RTOS applications, FPGA-based design, sensor networks, edge AI on microcontrollers, wearable health monitoring, smart agriculture, or similar). Complete hardware design/simulation and software/firmware development. Deliver fully working source code, circuit schematics, and a prototype demonstration (physical or simulation-based). Provide a detailed project report following standard academic form...

I am building a gaming-focused DMA solution that pairs custom FPGA/PCIe firmware with a Windows host application capable of safely reading live game memory—specifically for first-person shooters running on Windows 10 and Windows 11. The hardware side must be compatible with KMbox-style boards (or a comparable PCIe DMA card), while the software side needs an intuitive UI and a clean, well-documented API so additional tools can hook in later. On the firmware front, you’ll write HDL that handles high-speed memory acquisition, exposes a secure command set over PCIe, and keeps all traffic indistinguishable from ordinary bus activity. Solid knowledge of USB/PCIe link training, BAR mapping, and DMA engines is essential. The host application should be written in modern C++ or C...

I’m looking for a seasoned digital-logic professional who can step into my lab workflow, quickly understand the design challenges on my bench, and guide me from concept through verified implementation. The immediate need is flexible: you might end up drafting fresh schematics for a small FPGA-based subsystem, debugging timing faults in an existing logic chain, or simply showing me how to streamline test-bench simulations so I can spot issues earlier in the cycle. Your familiarity with tools such as MATLAB, LabVIEW, or VHDL/Verilog will be invaluable—feel free to lean on whichever environment you know best as long as it gets us to reliable, reproducible results. I’ll share all current documentation, measurement data, and constraints as soon as we connect so you c...

I need custom firmware for a PCIe-based DMA card so a second PC can attach to my Windows gaming rig, read or alter memory, and feed data back—yet look to both Windows and Fortnite’s anti-cheat as nothing more suspicious than a standard IDE ATA/ATAPI controller. The core goals are: • Mask all DMA activity and device signatures so common anti-cheat sweeps find only an ordinary storage controller. • Keep full, low-latency read / write access to physical memory from the host PC. • Allow on-the-fly interception or modification of data in transit when required. You’re free to start from an existing open-source project (e.g., PCILeech-compatible hardware) or write bare-metal code, as long as the finished image flashes cleanly to the card and survives stres...

FPGA RF transceiver design ,

TCD1304 CCD Sensor FPGA Project I am looking for a skilled freelancer to assist me in designing a TCD1304 CCD sensor FPGA project. The project requires the following: Sensor read the value of every pixel and creates a two dimensional array with the pixel number starting with the value above the threshold and the number of pixels above the threshold. 0-[0,0],1-[0,0]..112-[0,0],113-[345,20],114-[345,25],115-[345,30],116-[345,35]...311-[345,200],312-[345,205],313-[0.0],314-[0,0] The above data gives like Triangle image from the left position from 345, and top position can be 113 based on trigger. Also it says 312 is end position of the mark. From the above details, we are looking a FPGA solution that read the data from CCD Sensor and store approach 32Mb data then p...

I'm seeking an experienced FPGA developer who can assist with design and development, specifically in HDL coding, using both VHDL and Verilog. Ideal Skills and Experience: - Proficiency in both VHDL and Verilog - Strong background in FPGA architecture - Experience in integrating and interfacing FPGAs with other systems - Ability to test, debug, and optimize designs Please provide relevant project experience and a brief portfolio. Looking forward to your bids!

...Analysis (25% Commission) Budget: Commission-only. $0 upfront. You get 25% of every client you bring. Description: I need a sales partner to bring me clients. I do high-end supply chain risk analysis for space and defense: SPOF identification Monte Carlo disruption modeling Geopolitical scenario planning Supplier concentration analysis My work is proven. I have sample reports showing rad-hard FPGA concentration risk (48% market share, $890M disruption impact) and reaction wheel dependency mapping (38% of Western satellites affected). Target clients: Small defense contractors (50–500 employees) Space startups (post-Series A) Aerospace consulting firms Space insurance underwriters Private equity (defense/aerospace focus) Services to sell: One-off reports: €...

...evaluation and risk controls. Here’s what I have in mind: the quantum side tackles portfolio state-space exploration—think QAOA, VQE or amplitude-estimation—while TensorFlow / PyTorch models learn micro-structure patterns from live tick data and route only the most promising parameter sets back to the gate model. Latencies must stay sub-millisecond from signal to order, so a coherent design for GPU–FPGA–QPU orchestration is essential. Deliverables • A documented architecture diagram showing data flow between classical AI, middleware, and the chosen quantum SDK (Qiskit, Braket or similar). • Clean, modular Python code with C++/CUDA kernels where latency demands it, fully containerised for reproducibility. • Back-test and forward...

...updated design files (Altium or KiCad preferred), annotated schematics, and a concise report showing the projected performance gains plus any trade-offs introduced. Please highlight relevant projects you’ve done in hardware optimisation, especially if they involved tight timing budgets or high-speed buses. If you have your own test methodology or simulation tools (e.g., SPICE, SignalIntegrity, or FPGA prototyping) let me know; I’m open to integrating them into the workflow....

I need an experienced FPGA programmer to assist with a data processing application. Key Requirements: - Proficiency in at least one of the following FPGAs: Xilinx, Altera, Lattice - Expertise in data processing applications - Familiarity with VHDL, Verilog, or SystemVerilog Ideal Skills and Experience: - Proven track record in FPGA programming - Strong background in data processing algorithms - Ability to work with various FPGAs and HDLs Please provide relevant experience in your bids. We need to develop ethernet hub in fiber optic 2 ports , and 16 SPI for chip led controller using data and clock . SPecia Ethernet protocol defined by us.

...side: define an architecture that can see each chip as stacks move, bets slide, and pots grow, then pass clean data to the software team through a simple API or wired interface of your choice. Key expectations • Robust HF antenna array layout sized for a poker table, including multiplexing strategy to handle >100 simultaneous tags without collisions or dead zones. • Reader, controller, and MCU/FPGA selection with justification, full schematics and PCB files (Altium, KiCad, or similar). • Tag specification sized for standard casino chips, with guidance on orientation tolerance and shielding. • Firmware outline or example code that streams tag UID and RSSI fast enough for smooth betting actions. • Bill of materials, power budget, and wiring harn...