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    1,462 verilog projects proiecte găsite, la prețul de USD
    verilog programming S-a încheiat left

    verilog

    $384 (Avg Bid)
    $384 Oferta medie
    13 oferte

    fpga/ultra and xilinx wiznet vhdl/verilog

    $271 (Avg Bid)
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    15 oferte
    $52 Oferta medie
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    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

    $43 (Avg Bid)
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    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

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    4 oferte

    system verilog, uvm,synopsys expert

    $33 (Avg Bid)
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    6 oferte
    system verilog, uvm S-a încheiat left

    system verilog, uvm

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    Verilog S-a încheiat left

    Verilog

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    ...with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction Register 4- Control Unit 5- PC register 6- Shift logic unit 7- Conditional logic unit 8- Three-level Cache for the Data

    $351 (Avg Bid)
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    4 oferte

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $47 (Avg Bid)
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    5 oferte

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

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    7 oferte

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
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    4 oferte
    verilog counter S-a încheiat left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    $62 (Avg Bid)
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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [conectează-te pentru a consulta linkul URL] file.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $759 (Avg Bid)
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    1 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $189 - $567
    $189 - $567
    0 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $565 (Avg Bid)
    $565 Oferta medie
    1 oferte

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    $296 (Avg Bid)
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    11 oferte

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $628 (Avg Bid)
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    23 oferte
    Vivado Expert S-a încheiat left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    $27 / hr (Avg Bid)
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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    3 oferte

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1689 (Avg Bid)
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    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

    $1282 (Avg Bid)
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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    $108 (Avg Bid)
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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $750 (Avg Bid)
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    1 oferte

    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

    $776 (Avg Bid)
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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

    $16 / hr (Avg Bid)
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    VHDL or Verilog program S-a încheiat left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    1 oferte

    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

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    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1031 (Avg Bid)
    $1031 Oferta medie
    4 oferte

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [conectează-te pentru a consulta linkul URL]; a. The source can

    $625 (Avg Bid)
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    3 oferte
    find fpga projects S-a încheiat left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $462 (Avg Bid)
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    10 oferte
    Matlab Codnig S-a încheiat left

    I need the matlab developer and verilog developer

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    16-point FFT S-a încheiat left

    verilog code for radix-4 16 point fft

    $15 (Avg Bid)
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    8 oferte

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    $16 (Avg Bid)
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    4 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $11834 (Avg Bid)
    $11834 Oferta medie
    2 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $10690 (Avg Bid)
    $10690 Oferta medie
    1 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $894 - $901
    $894 - $901
    0 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $882 - $882
    $882 - $882
    0 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $884 - $884
    $884 - $884
    0 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $933 (Avg Bid)
    $933 Oferta medie
    3 oferte

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $736 - $883
    $736 - $883
    0 oferte
    reviewing a code S-a încheiat left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

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    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    $150 (Avg Bid)
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    LUT optimization of FFT S-a încheiat left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

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    Verilog Expert S-a încheiat left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

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    20 oferte

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    $35 (Avg Bid)
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