Verilog vhdl vergleichproiecte

Filtrare

Căutările mele recente
Filtrează în funcție de:
Buget
la
la
la
Tip
Aptitudini
Limbi
    Starea proiectului
    2,000 verilog vhdl vergleich proiecte găsite, la prețul de USD
    Aparat de cafea in VHDL S-a încheiat left

    Crearea unui aparat de cafea in VHDL(rulabil in programul Vivado) intr-un limbaj cat mai simplist indeplinind cerintele din documentul atasat.

    $8 (Avg Bid)
    $8 Oferta medie
    3 oferte
    Debuging verilog S-a încheiat left

    Debuging verilog

    $60 (Avg Bid)
    $60 Oferta medie
    1 oferte

    السلام عليكم ورحمة الله وبركاته واسعد الله اوقاتك بكل خير عندي واجب ومحتاج مساعدتك اذا وقتك يسمح. انشاء بروجكت بال verilog بحيث يقرأ محتويات ال ROM ويخرج المحتوى على LEDs

    $50 (Avg Bid)
    $50 Oferta medie
    1 oferte

    Modul de inmultire, folosind sumator si registrii de deplasare

    $101 (Avg Bid)
    $101 Oferta medie
    10 oferte

    Este un proiect pentru facultate. Termenul este 17 mai 2021. Cerința detaliată a proiectului este în imagine. Mi-ar trebui documentația care să cuprindă cutia neagră a circuitului, descompunerea în Unitate de control și Unitate de Execuție, o listă cu resursele pe care le voi volosi (ex: generator de numere aleatoare), organigrama, implementare in VHDL și o schema logică pentru că prezentarea proiectului trebuie făcută în Logisim, în care nu putem folosi decât componente de bază. Trebuie să folosim afișorul cu 7 segmente, butoane și switch-uri. La finalul documentației ar trebui să fie și Justificarea soluției alese, Manual de utilizare și întreținere, dar și Posibilități de dezvoltare ulterioară.

    $72 (Avg Bid)
    $72 Oferta medie
    1 oferte
    Project for Athul B. S-a încheiat left

    Hi Athul B.,verilog help

    $20 (Avg Bid)
    $20 Oferta medie
    1 oferte
    $20 Oferta medie
    1 oferte
    Project for Ankita L. S-a încheiat left

    verilog programming

    $7 - $7
    $7 - $7
    0 oferte
    $25 Oferta medie
    1 oferte
    Design Verification S-a încheiat left

    PCle, ethernet , UVM, System Verilog

    $130 (Avg Bid)
    $130 Oferta medie
    2 oferte
    verilog programming S-a încheiat left

    verilog

    $393 (Avg Bid)
    $393 Oferta medie
    12 oferte

    fpga/ultra and xilinx wiznet vhdl/verilog

    $229 (Avg Bid)
    $229 Oferta medie
    14 oferte
    $52 Oferta medie
    2 oferte

    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

    $34 (Avg Bid)
    $34 Oferta medie
    5 oferte

    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

    $28 (Avg Bid)
    $28 Oferta medie
    3 oferte

    system verilog, uvm,synopsys expert

    $26 (Avg Bid)
    $26 Oferta medie
    6 oferte
    system verilog, uvm S-a încheiat left

    system verilog, uvm

    $43 (Avg Bid)
    $43 Oferta medie
    8 oferte
    Verilog S-a încheiat left

    Verilog

    $162 (Avg Bid)
    $162 Oferta medie
    3 oferte
    Scriere si testare VHDL S-a încheiat left

    Trebuie sa programez o placa Spartan-3 Board sa afiseze o imagine pe un LCD ( 2.4 LCD cu driverul de ILI9341) . Imaginea va fi primita pe seriala de RS-232 si transmisa pe LCD , dupa ce LCD-ul a fost initializat . Pana acum am implementat core-ul de SPI ( protocolul prin care comunica placa cu LCD-ul ) , core-ul de seriala ( la care vine atasat un buffer pt a putea verifica aparitia datelor pe seriala si a prelua datele) si s-a creat un bloc de control ( in fapt este o masina de stari) care initializeaza LCD-ul (si am putut "desena"(hard-coded) un dreptunghi colorat pe LCD). Ceea ce am nevoie este ca imaginea trimisa pe seriala sa fie afisata pe LCD ( incercari esuate din partea mea ).

    $250 (Avg Bid)
    $250 Oferta medie
    1 oferte

    Intr-un proiect VHDL sa se realizeze un simulator de memorie CACHE (cu mai multe politici de scriere si citire) care sa poata fi testat pe FPGA. Pretul si durata proiectului sunt orientative.

    $224 (Avg Bid)
    $224 Oferta medie
    1 oferte

    Intr-un proiect VHDL sa se realizeze un simulator de memorie CACHE (cu mai multe politici de scriere si citire) care sa poata fi testat pe FPGA. Pretul si durata proiectului sunt orientative.

    $100 (Avg Bid)
    $100 Oferta medie
    1 oferte

    Composto de 7 segmentos de LEDs que podem ser acionados individualmente. Diagrama de blocos, Linguagem VHDL. Trabalho que visa a programção de um display 7 segmentos, o ponto é: temos os codigos prontos e a maneira como deve ficar o diagrama de blocos. Estamos procurando alguem para nos ajudar na criação do diagrama de bloco para cada programação e no final, juntar cada diagrama/programação em um só sistema, como também temos uma imagem de como devem ficar. Utilizando o programa Quartus II e VHDL. Temos um pdf de passo a passo de cada programação e uma imagem de como cada programação deve ficar o seu diagrama de blocos.

    $159 (Avg Bid)
    $159 Oferta medie
    5 oferte

    **Projektbeschreibung:** Wir suchen einen erfahrenen Excel-Spezialisten, der uns dabei hilft, aus 20 verschiedenen (aber gleich aufgebauten) Excel-Listen eine konsolidierte Kundenliste zu erstellen. Die Aufgabe umfasst folgende Schritte: 1. **Vergleich der Excel-Listen:** Die 20 Excel-Listen mit insgesamt ca. 35.000 Kunden sollen miteinander verglichen werden, um Duplikate zu finden. 2. **Entfernung von Duplikaten:** Identifizierte Duplikate sollen entfernt werden, sodass jeder Eintrag nur einmal vorhanden ist. 3. **Zusammenführung der Listen:** Die bereinigten Listen sollen in eine einzige Liste zusammengeführt werden. **Anforderungen:** - Erfahrung im Umgang mit Excel und Datenmanipulation. - Fähigkeit, komplexe Excel-Funktionen zu verwenden, um Duplikate zu ide...

    $1093 (Avg Bid)
    $1093 Oferta medie
    47 oferte

    I'm seeking a competent Verilog/VHDL developer to create an image processor for scientific imaging. The primary focus of the processor is noise removal, specifically salt and pepper noise. Key Requirements: - Noise Removal: The processor must effectively remove salt and pepper noise from the input images. This is crucial for the intended application in scientific imaging. - Real-time Processing: The design should ideally support real-time processing for seamless image enhancement. - Deadline: This is an urgent project with a tight 2-3 day deadline. Punctuality is paramount. Ideal Skills and Experience: - Proficiency in Verilog/VHDL: Extensive experience in Verilog/VHDL development is necessary to tackle this project effectively. - Image Pro...

    $111 (Avg Bid)
    $111 Oferta medie
    6 oferte

    I'm in need of a VHDL expert to design a robust ONFI controller for interfacing with NAND flash memory. The controller is expected to include the following key features: - Read Operation: The controller should be capable of initiating and managing read operations from the connected NAND flash memory. - Write Operation: The controller should be able to write data to the NAND flash memory reliably and efficiently. - Command Interface: The ONFI controller should have a user-friendly and practical command interface for seamless control. Ideal candidates for this project should have: - Proficiency in VHDL programming language - Extensive experience in FPGA design, particularly in developing memory controllers - Past experience working with NAND flash memory and ONFI specifi...

    $28 / hr (Avg Bid)
    $28 / hr Oferta medie
    4 oferte

    I'm looking for an expert in Verilog/FPGA to implement an Isometric Shooter Game on Terasic's DE1-SoC model. Key Requirements: - Verilog Implementation: The core of the project is the translation of the game logic into Verilog. This includes the game mechanics, player controls, enemy AI, and shooting functionality. - FPGA Specifics: The implementation should be optimized for the DE1-SoC FPGA model. - Game Features: The game should be similar to Space Invaders, with an isometric perspective. This includes player movement, enemy AI, and shooting mechanics. Deliverables: - Fully Functional Game: The Verilog code should be efficient, bug-free, and provide the expected gameplay experience. - Documentation: All codes should be well documented and expl...

    $13 (Avg Bid)
    $13 Oferta medie
    5 oferte
    Vlsi xschem ngspice S-a încheiat left

    Hi, Take a look at this project: ...should have digital blocks just like the above and then synthesized and integrated with the analog components like comparators, buffers, etc, basically very similar to the above project. Or 2) Just reproduce the above GitHub project such that it is less complicated but it should be 12 bit like before. I should be able to understand it. I tried it myself but there were some problems like in verilog to spice conversation and some spice files giving errors and most simulation getting stuck because it takes too much time 1) or 2) you may do any one whichever seems possible. Note that it is for my self learning purposes and any help regarding reproducing it or understanding it or learning to simulate it will be beneficial for me and I will pay ac...

    $95 (Avg Bid)
    $95 Oferta medie
    1 oferte

    Job Description: We are searching for an exceptional RTL Design Specialist specializing in ASIC/VLSI to play a ...optimized for LLM training and benchmarking. Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes. Job Requirements: BS or MS degree in Electrical Engineering or a related field. 3-5 years of proven experience in hardware design development. RTL design specialization in ASIC/VLSI. Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC. Expertise in scripting, front-end, and verification workflows, and integrations within the hardware design environment. Exceptional problem-solving, communication, and collaborative skills. Familiarity with Synopsys/Cadence or o...

    $1197 (Avg Bid)
    $1197 Oferta medie
    3 oferte

    ...Responsibilities: - Hardware design: You'll be responsible for creating and implementing hardware designs, including system architecture, chip layout, and integration. - Enhancing LLMs: Your primary focus will be on optimizing and enhancing the LLMs using your ASIC/VLSI, and Verilog/SystemVerilog/VHDL/SystemC expertise. Ideal Skills and Experience: - A strong background in Electrical Engineering, with a Bachelor's or Master's degree. - 3-5 years of experience in the field of ASIC/VLSI design. - Proficiency in Verilog/SystemVerilog, VHDL, and SystemC. - Previous experience in enhancing LLMs would be a strong advantage. This role is ideal for someone with a keen interest in hardware design and a passion for creating innovative solutions. If you...

    $3719 (Avg Bid)
    $3719 Oferta medie
    7 oferte

    I'm seeking intermediate-level electrical engineers for a long-term project. The ideal candidate should have a good grasp of circuit design, power system analysis, control system development, as well as experience in PCB design, Arduino, FPGA, Raspberry Pi, and Verilog/VHDL. Key responsibilities: - Circuit design, power system analysis, and control system development - Proficiency in MATLAB/Simulink for simulations and modeling - Expertise in EAGLE or Altium for PCB design - Knowledge of Verilog/VHDL for FPGA development This role might be a great fit for someone with an academic background in electrical engineering, a few years of industry experience, and a solid portfolio of relevant projects. The work is ongoing and offers a variety of tasks, so adapt...

    $112 (Avg Bid)
    $112 Oferta medie
    12 oferte

    Seeking a proficient RTL design engineer to assist with a block-level design project. Your daily tasks will include Linting, CDC analysis, and Synthesis. Expertise is required in Verilog, the preferred hardware description language for this assignment. Required Skills and Experience: - Exceptional competence in RTL design - Proven experience in Linting, CDC analysis, and Synthesis - Proficiency in Verilog - Experience in block-level design preferred I look forward to collaborating with an engineer who will contribute valuable insight and expertise towards achieving the project objectives.

    $3 / hr (Avg Bid)
    $3 / hr Oferta medie
    11 oferte

    ...Large-Scale Integration) architecture that is designed to classify Atrial Fibrillation for wearable devices. This ambitious project requires specialised expertise and precise execution. Key Tasks: - The design of a Low-Power, DNN-Based VLSI architecture, which is yet to be initiated. - Create a Full Custom VLSI that is suited for classifying Atrial Fibrillation. Ideal Skills and Experience: -Verilog. -FPGA. - Relevant experience and extensive knowledge of designing Full Custom VLSI architectures. - Proven expertise in VLSI architectures and their relation to wearable device technology. - Firm understanding of Atrial Fibrillation classification. - Familiarity with power optimisation in VLSI designs would be an advantage, although not a requirement. Candidates who can apply th...

    $64 (Avg Bid)
    $64 Oferta medie
    5 oferte

    As part of this project, I need assistance in performing the following tasks: - Writing VHDL code - Designing FPGA circuits, specifically for Xilinx FPGA The goal is to achieve PWM via VHDL and PS to PL UART communication in the FPGA circuit design. It would be advantageous if you have a strong background in VHDL, FPGA circuit design and specific experience with Xilinx FPGA. Additionally, understanding of PWM and UART communication would be beneficial. Estoy buscando un ingeniero FPGAs y firmware para q haga un pequeño proyecto para hacerlo correr en una tarjeta de desarrollo Pynq-Z2 con el Sw Vivado. Se trata de implementar un PWM de valor de entrada variable, esto en VHDL para cargarlo en la PL de la Zynq. Se trataría de lo siguiente; a tr...

    $143 / hr (Avg Bid)
    Acord de confidenţialitate
    $143 / hr Oferta medie
    8 oferte

    I'm in need of a Verilog expert proficient with Quartus Prime Toolchain. Key Requirements: - Professional with Verilog: Need someone experienced in designing digital circuits and implementing specific functionalities using Verilog. - Proficiency with Quartus Prime: Familiarity with the Quartus Prime Toolchain is a must. I need to design, simulate, implement and test a digital circuit using the Quartus Prime toolchain as per the specifications I will provide and demonstrate the workflow when using the Verilog HDL to construct a design for a physical Field Programmable Gate Array (FPGA) target. Please apply if you have the required expertise. No teams or companies please.

    $112 (Avg Bid)
    $112 Oferta medie
    10 oferte

    We are looking for an experienced freelancer to create a custom DMA firmware using this simple guide : The guide provides detailed instructions, but I lack the time to complete it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone pr...it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone proficient. **Tasks:** - Configure and customize firmware based on pcileech-fpga - Use Vivado for development - Emulate TLP and configure the configuration space **Required Skills:** - FPGA design and programming - Experience with Vivado (Xilinx) - DMA firmware development - Verilog/VHDL programming - Debugging and testing embedded systems

    $211 (Avg Bid)
    $211 Oferta medie
    9 oferte

    I am looking for an experienced Verilog developer who can work on my Verilo HDL project. Design a digital circuit for a fruit sorter based on following specification. Develop the block diagram (consists of datapath and control units) and the ASMD chart. Assume that there is a 1-bit RESET signal to reset the circuit and it is asynchronous and active low. In addition, there is a 1-bit CLOCK as the clock. The circuit will start the operation when a 1-bit input signal START is asserted. A fruit detector provides a 1-bit input FRUIT that becomes 1 for one clock cycle if banana is detected and the FRUIT signal will be 1 for two clock cycles if orange is detected. There are 2 different outputs which are OUT1 and OUT2 that will be 1 for one clock cycle for the type of frui...

    $70 (Avg Bid)
    $70 Oferta medie
    1 oferte

    ...into Verilog and run on FPGA device using HLS Vitis. The existing project has: - Edge detection capabilities - Image segmentation capabilities The primary goal of this project is not to enhance or alter the images, but to convert the existing codebase from C++ to Verilog, utilizing HLS Vitis. With your expertise: - Maintain the integrity of the current functionalities during conversion - Reframe the C++ code to Verilog language ensuring a seamless running on an FPGA device. The successful bidder should have significant experience with Verilog, C++, and HLS Vitis, as well as a good understanding of Image Processing algorithms, especially Edge Detection and Image Segmentation. The final output of the conversion should result in an image file product. The d...

    $381 (Avg Bid)
    $381 Oferta medie
    12 oferte

    I'm currently seeking an individual who is not only proficient in VHDL coding but also in Quartus design implementation. Key Responsibilities: - Work on specific tasks related to VHDL coding - Implement design using Quartus While the overall aim of the project and the timeline aren't specified yet, I am eager to work with someone who is flexible and can adapt as per project needs. The ideal candidate for this role should be based in Pakistan, knowledgeable in FPGA programming, dependable, efficient, and proactive when it comes to troubleshooting and problem-solving.

    $409 (Avg Bid)
    $409 Oferta medie
    6 oferte

    Greetings, We are assembling a dynamic team and currently seeking 4-5 proficient Electrical Engineers to join us for a long-term collaboration. This opportunity is ideal for individuals with expertise in electronics, power systems, and communication systems. Key Requirements: - Strong command over MATLAB for data analysis, simulation, and modeling. - Proficiency in VHDL and Verilog for hardware description and digital circuit design. - Experience with multisim or similar simulation software for circuit analysis and design verification. This collaboration offers an exciting chance to work on diverse projects spanning electronics, power systems, and communication systems. We are committed to fostering a collaborative environment that encourages innovation and professional gr...

    $11 / hr (Avg Bid)
    $11 / hr Oferta medie
    14 oferte

    I need verilog code,testbench and simulation for this duty : Design a vector processing system that performs dot product of two vectors kept in the memory. The length of the vector is given as an input and at each clock cycle one element from each vector is multiplied and added. At the end of the processing a valid signal will be raised along with the result. Elements of the vectors are 8-bit unsigned vectors.

    $118 (Avg Bid)
    $118 Oferta medie
    10 oferte

    I'm seeking a VHDL expert for a college project revolving around basic logic gates. The project involves primarily circuit design, with an emphasis on the following: - The project is centred around basic logic gates (AND, OR, NOT) - so the complexity level is relatively beginner-friendly - A key part of this task is the delivery of comprehensive project documentation along with the circuit design. This will help me understand the design process and the logic behind it. If you have experience in VHDL and can deliver both the circuit design and documentation, I'd love to hear from you. Please include details of similar projects you've worked on, as well as your experience level with VHDL.

    $14 / hr (Avg Bid)
    $14 / hr Oferta medie
    15 oferte

    Im working on a c++ image processing project , and i need to convert my C++ code to Verilog using HLS vitis , then implement it to run on Ultra96v2 Xilinx FPGA board .

    $470 (Avg Bid)
    $470 Oferta medie
    15 oferte

    I'm in need of skilled programmers to develop interfaces for my Place and Route EDA flows. The ideal candidate will have experience in the following: - Proficiency in Python and/or C++ - Familiarity with VHDL, Verilog, and SystemVerilog - Experience in file input generation - Strong file parsing capabilities - Ability to manage EDA flows using TCL The interfaces need to be able to handle the entire EDA flow, from file input generation to error reporting. Experience in developing similar interfaces will be a big advantage. Please include relevant work samples in your bid.

    $26 / hr (Avg Bid)
    $26 / hr Oferta medie
    29 oferte

    I'm in urgent need of skilled VHDL/Quartus professionals from Pakistan for a project. I will clarify the specifics once a mutual understanding and agreement is reached. Ideal skills for the job include: - Proficiency in VHDL/Quartus - Ability to design, troubleshoot and optimize digital circuits - Ability to work independently or with minimal supervision - Excellent communication skills to effectively explain intricate concepts or problems Experience level can range from beginner to expert. The expectation, however, is the ability to deliver quality work within the stipulated time-frame.

    $210 (Avg Bid)
    $210 Oferta medie
    4 oferte

    I am currently working on a traffic light project and I need the expertise of a VHDL programming guru. Someone who has had previous experience programming the FPGA DEO Nano development board would be a perfect fit, as that's what I am specifically working with. I am using VHDL to code for the EP4CE22F17C6N board. The base of my project, using a state machine, has already been created. As far as the hardware end of things, I've already prepared the circuit diagram and have started with LED lights and toggle switches. But I do need to make some changes in it as the requirement in order to make it more complex for that I need someone who can do the following additions or changes in the project that I have attached in my zip folder to work exactly as described in the ...

    $143 (Avg Bid)
    $143 Oferta medie
    7 oferte
    10000 S-a încheiat left

    Stepper motor controller in FPGA which generates pulses according to command. verilog code

    $120 (Avg Bid)
    $120 Oferta medie
    1 oferte

    hello, I have a project and I'm stuck at some point, please see the specifications in the zip it's for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering...for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering 2 of the project, now for rendering 3, I just need to modify the block diagrams, the truth table, the state graph and the memory map (which are all done during rendering 1) according to the modifications requested by the workbook. load... We don't need coding in vhdl, just make the modifications on rendering 1 according to the instructions for rendering 3 if ever we can do a 10 minute meeting to e...

    $20 (Avg Bid)
    $20 Oferta medie
    2 oferte

    I'm seeking an experienced trainer for Spyglass tool, with a concentration on Lint and CDC (Clock Domain Crossing). As beginners in Spyglass and proficient in Verilog, we primarily aim to identify and fix coding errors through this training. Ideal Skills and Experience: - Strong knowledge of Lint and CDC in Spyglass tool - Demonstrated experience in coding and debugging in Verilog - Excellent training skills - Ability to create and simplify complex concepts for beginners.

    $11 / hr (Avg Bid)
    $11 / hr Oferta medie
    5 oferte

    ...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...

    $180 (Avg Bid)
    $180 Oferta medie
    12 oferte

    ...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...

    $97 (Avg Bid)
    $97 Oferta medie
    4 oferte