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    4,820 verilog vhdl proiecte găsite, la prețul de USD
    Aparat de cafea in VHDL S-a încheiat left

    Crearea unui aparat de cafea in VHDL(rulabil in programul Vivado) intr-un limbaj cat mai simplist indeplinind cerintele din documentul atasat.

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    Debuging verilog S-a încheiat left

    Debuging verilog

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    السلام عليكم ورحمة الله وبركاته واسعد الله اوقاتك بكل خير عندي واجب ومحتاج مساعدتك اذا وقتك يسمح. انشاء بروجكت بال verilog بحيث يقرأ محتويات ال ROM ويخرج المحتوى على LEDs

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    Modul de inmultire, folosind sumator si registrii de deplasare

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    Este un proiect pentru facultate. Termenul este 17 mai 2021. Cerința detaliată a proiectului este în imagine. Mi-ar trebui documentația care să cuprindă cutia neagră a circuitului, descompunerea în Unitate de control și Unitate de Execuție, o listă cu resursele pe care le voi volosi (ex: generator de numere aleatoare), organigrama, implementare in VHDL și o schema logică pentru că prezentarea proiectului trebuie făcută în Logisim, în care nu putem folosi decât componente de bază. Trebuie să folosim afișorul cu 7 segmente, butoane și switch-uri. La finalul documentației ar trebui să fie și Justificarea soluției alese, Manual de utilizare și întreținere, dar și Posibilități de dezvoltare ulterioară.

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    Project for Athul B. S-a încheiat left

    Hi Athul B.,verilog help

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    Project for Ankita L. S-a încheiat left

    verilog programming

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    Design Verification S-a încheiat left

    PCle, ethernet , UVM, System Verilog

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    verilog programming S-a încheiat left

    verilog

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    fpga/ultra and xilinx wiznet vhdl/verilog

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    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

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    system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script system verilog, uvm, Script

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    system verilog, uvm,synopsys expert

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    system verilog, uvm S-a încheiat left

    system verilog, uvm

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    Verilog S-a încheiat left

    Verilog

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    Scriere si testare VHDL S-a încheiat left

    Trebuie sa programez o placa Spartan-3 Board sa afiseze o imagine pe un LCD ( 2.4 LCD cu driverul de ILI9341) . Imaginea va fi primita pe seriala de RS-232 si transmisa pe LCD , dupa ce LCD-ul a fost initializat . Pana acum am implementat core-ul de SPI ( protocolul prin care comunica placa cu LCD-ul ) , core-ul de seriala ( la care vine atasat un buffer pt a putea verifica aparitia datelor pe seriala si a prelua datele) si s-a creat un bloc de control ( in fapt este o masina de stari) care initializeaza LCD-ul (si am putut "desena"(hard-coded) un dreptunghi colorat pe LCD). Ceea ce am nevoie este ca imaginea trimisa pe seriala sa fie afisata pe LCD ( incercari esuate din partea mea ).

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    Intr-un proiect VHDL sa se realizeze un simulator de memorie CACHE (cu mai multe politici de scriere si citire) care sa poata fi testat pe FPGA. Pretul si durata proiectului sunt orientative.

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    Intr-un proiect VHDL sa se realizeze un simulator de memorie CACHE (cu mai multe politici de scriere si citire) care sa poata fi testat pe FPGA. Pretul si durata proiectului sunt orientative.

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    Seeking a proficient RTL design engineer to assist with a block-level design project. Your daily tasks will include Linting, CDC analysis, and Synthesis. Expertise is required in Verilog, the preferred hardware description language for this assignment. Required Skills and Experience: - Exceptional competence in RTL design - Proven experience in Linting, CDC analysis, and Synthesis - Proficiency in Verilog - Experience in block-level design preferred I look forward to collaborating with an engineer who will contribute valuable insight and expertise towards achieving the project objectives.

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    ...Large-Scale Integration) architecture that is designed to classify Atrial Fibrillation for wearable devices. This ambitious project requires specialised expertise and precise execution. Key Tasks: - The design of a Low-Power, DNN-Based VLSI architecture, which is yet to be initiated. - Create a Full Custom VLSI that is suited for classifying Atrial Fibrillation. Ideal Skills and Experience: -Verilog. -FPGA. - Relevant experience and extensive knowledge of designing Full Custom VLSI architectures. - Proven expertise in VLSI architectures and their relation to wearable device technology. - Firm understanding of Atrial Fibrillation classification. - Familiarity with power optimisation in VLSI designs would be an advantage, although not a requirement. Candidates who can apply th...

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    As part of this project, I need assistance in performing the following tasks: - Writing VHDL code - Designing FPGA circuits, specifically for Xilinx FPGA The goal is to achieve PWM via VHDL and PS to PL UART communication in the FPGA circuit design. It would be advantageous if you have a strong background in VHDL, FPGA circuit design and specific experience with Xilinx FPGA. Additionally, understanding of PWM and UART communication would be beneficial. Estoy buscando un ingeniero FPGAs y firmware para q haga un pequeño proyecto para hacerlo correr en una tarjeta de desarrollo Pynq-Z2 con el Sw Vivado. Se trata de implementar un PWM de valor de entrada variable, esto en VHDL para cargarlo en la PL de la Zynq. Se trataría de lo siguiente; a tr...

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    Acord de confidenţialitate
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    I'm in need of a Verilog expert proficient with Quartus Prime Toolchain. Key Requirements: - Professional with Verilog: Need someone experienced in designing digital circuits and implementing specific functionalities using Verilog. - Proficiency with Quartus Prime: Familiarity with the Quartus Prime Toolchain is a must. I need to design, simulate, implement and test a digital circuit using the Quartus Prime toolchain as per the specifications I will provide and demonstrate the workflow when using the Verilog HDL to construct a design for a physical Field Programmable Gate Array (FPGA) target. Please apply if you have the required expertise. No teams or companies please.

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    We are looking for an experienced freelancer to create a custom DMA firmware using this simple guide : The guide provides detailed instructions, but I lack the time to complete it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone pr...it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone proficient. **Tasks:** - Configure and customize firmware based on pcileech-fpga - Use Vivado for development - Emulate TLP and configure the configuration space **Required Skills:** - FPGA design and programming - Experience with Vivado (Xilinx) - DMA firmware development - Verilog/VHDL programming - Debugging and testing embedded systems

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    I am looking for an experienced Verilog developer who can work on my Verilo HDL project. Design a digital circuit for a fruit sorter based on following specification. Develop the block diagram (consists of datapath and control units) and the ASMD chart. Assume that there is a 1-bit RESET signal to reset the circuit and it is asynchronous and active low. In addition, there is a 1-bit CLOCK as the clock. The circuit will start the operation when a 1-bit input signal START is asserted. A fruit detector provides a 1-bit input FRUIT that becomes 1 for one clock cycle if banana is detected and the FRUIT signal will be 1 for two clock cycles if orange is detected. There are 2 different outputs which are OUT1 and OUT2 that will be 1 for one clock cycle for the type of frui...

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    ...into Verilog and run on FPGA device using HLS Vitis. The existing project has: - Edge detection capabilities - Image segmentation capabilities The primary goal of this project is not to enhance or alter the images, but to convert the existing codebase from C++ to Verilog, utilizing HLS Vitis. With your expertise: - Maintain the integrity of the current functionalities during conversion - Reframe the C++ code to Verilog language ensuring a seamless running on an FPGA device. The successful bidder should have significant experience with Verilog, C++, and HLS Vitis, as well as a good understanding of Image Processing algorithms, especially Edge Detection and Image Segmentation. The final output of the conversion should result in an image file product. The d...

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    I'm currently seeking an individual who is not only proficient in VHDL coding but also in Quartus design implementation. Key Responsibilities: - Work on specific tasks related to VHDL coding - Implement design using Quartus While the overall aim of the project and the timeline aren't specified yet, I am eager to work with someone who is flexible and can adapt as per project needs. The ideal candidate for this role should be based in Pakistan, knowledgeable in FPGA programming, dependable, efficient, and proactive when it comes to troubleshooting and problem-solving.

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    Greetings, We are assembling a dynamic team and currently seeking 4-5 proficient Electrical Engineers to join us for a long-term collaboration. This opportunity is ideal for individuals with expertise in electronics, power systems, and communication systems. Key Requirements: - Strong command over MATLAB for data analysis, simulation, and modeling. - Proficiency in VHDL and Verilog for hardware description and digital circuit design. - Experience with multisim or similar simulation software for circuit analysis and design verification. This collaboration offers an exciting chance to work on diverse projects spanning electronics, power systems, and communication systems. We are committed to fostering a collaborative environment that encourages innovation and professional gr...

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    The goal of this project is using Vivado tools to enable a hardware implementation on an FPGA board. The key requirement from the FPGA board is high computational speed. Therefore, proficiency in Verilog language is preferred as I intend to implement the NTT algorithm. I am looking for a developer who is experienced with FPGA boards and Vivado tools. The chosen freelancer should also have the ability to maximize computing capabilities of the board for the said implementation.

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    I need verilog code,testbench and simulation for this duty : Design a vector processing system that performs dot product of two vectors kept in the memory. The length of the vector is given as an input and at each clock cycle one element from each vector is multiplied and added. At the end of the processing a valid signal will be raised along with the result. Elements of the vectors are 8-bit unsigned vectors.

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    I'm seeking a VHDL expert for a college project revolving around basic logic gates. The project involves primarily circuit design, with an emphasis on the following: - The project is centred around basic logic gates (AND, OR, NOT) - so the complexity level is relatively beginner-friendly - A key part of this task is the delivery of comprehensive project documentation along with the circuit design. This will help me understand the design process and the logic behind it. If you have experience in VHDL and can deliver both the circuit design and documentation, I'd love to hear from you. Please include details of similar projects you've worked on, as well as your experience level with VHDL.

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    I need a talented RTL designer, proficient in Verilog, to carry out an NTT Implementation project focused on dataflow modeling. Key Requirements: - Expertise in Verilog, with a deep understanding and application of dataflow modeling - Prior experience in RTL design and synthesis - The main goal for this task is to achieve optimization of the design using your Verilog expertise - Attention to detail, punctuality, and efficient communication skills are a must This project offers an opportunity to work with an interesting model and explore optimized NTT implementation. Your contribution to this project will be influential in achieving an optimized design.

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    Im working on a c++ image processing project , and i need to convert my C++ code to Verilog using HLS vitis , then implement it to run on Ultra96v2 Xilinx FPGA board .

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    I'm in need of skilled programmers to develop interfaces for my Place and Route EDA flows. The ideal candidate will have experience in the following: - Proficiency in Python and/or C++ - Familiarity with VHDL, Verilog, and SystemVerilog - Experience in file input generation - Strong file parsing capabilities - Ability to manage EDA flows using TCL The interfaces need to be able to handle the entire EDA flow, from file input generation to error reporting. Experience in developing similar interfaces will be a big advantage. Please include relevant work samples in your bid.

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    I'm in urgent need of skilled VHDL/Quartus professionals from Pakistan for a project. I will clarify the specifics once a mutual understanding and agreement is reached. Ideal skills for the job include: - Proficiency in VHDL/Quartus - Ability to design, troubleshoot and optimize digital circuits - Ability to work independently or with minimal supervision - Excellent communication skills to effectively explain intricate concepts or problems Experience level can range from beginner to expert. The expectation, however, is the ability to deliver quality work within the stipulated time-frame.

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    I am currently working on a traffic light project and I need the expertise of a VHDL programming guru. Someone who has had previous experience programming the FPGA DEO Nano development board would be a perfect fit, as that's what I am specifically working with. I am using VHDL to code for the EP4CE22F17C6N board. The base of my project, using a state machine, has already been created. As far as the hardware end of things, I've already prepared the circuit diagram and have started with LED lights and toggle switches. But I do need to make some changes in it as the requirement in order to make it more complex for that I need someone who can do the following additions or changes in the project that I have attached in my zip folder to work exactly as described in the ...

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    10000 S-a încheiat left

    Stepper motor controller in FPGA which generates pulses according to command. verilog code

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    hello, I have a project and I'm stuck at some point, please see the specifications in the zip it's for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering...for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering 2 of the project, now for rendering 3, I just need to modify the block diagrams, the truth table, the state graph and the memory map (which are all done during rendering 1) according to the modifications requested by the workbook. load... We don't need coding in vhdl, just make the modifications on rendering 1 according to the instructions for rendering 3 if ever we can do a 10 minute meeting to e...

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    I'm seeking an experienced trainer for Spyglass tool, with a concentration on Lint and CDC (Clock Domain Crossing). As beginners in Spyglass and proficient in Verilog, we primarily aim to identify and fix coding errors through this training. Ideal Skills and Experience: - Strong knowledge of Lint and CDC in Spyglass tool - Demonstrated experience in coding and debugging in Verilog - Excellent training skills - Ability to create and simplify complex concepts for beginners.

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    ...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...

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    ...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...

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    I am in need of a seasoned FPGA programmer, proficient in Verilog and Vivado, who can build and run a program for me on a ZYNQ 7000 FPGA board. Our primary goal is: - To work on a program that performs Homomorphic Encryption Algorithm, by analysing its architecture - You'll need to identify the blocks responsible for addition and multiplication operations, as well as enumerate all IO used for these operations. Ideal candidate should have: - Extensive experience in conveying complex FPGA architectures in an understandable form - Proficiency in using Vivado for hardware simulation

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    I'm seeking a skilled FPGA developer to construct an intermediate-level chessAI project. The AI is expected to run real-time on a Spartan-7 FPGA board, using Vivado and Vitis. Key Project Details: - **Real-time Performance:** The AI should be optimised for real-time operation on the FPGA board. - **Intermediate Complexity:** The chessAI should be capable of intermediate-level game play, providing engaging and challenging performance. - **FPGA Model:** The project is designed for a Spartan-7 FPGA board, hence prior experience with this model is preferable. Key Skill Requirements: - Proficiency in FPGA development, particularly with Vivado and Vitis. - Prior experience in designing chessAI or comparable AI projects. - Expertise in optimising AI models for real-time FPGA implementation...

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    DEADLINE 21st I need an Object Detection(displays text on screen of object name) & Live Streaming system(records video when switch or button pressed), all to be implemented on a Zybo Z7 board with a pcam 5c camera module. Here are the details: - **Programming Language**: The system needs to be developed using verilog and xlinx tools. - **Standalone or Integrated**: I'm looking for the Object Detection & Live Streaming system to be integrated with zyboz7 and pcam5c. - **Functionality**: The system should perform real-time object detection and identification, as well as record and store live streams for later analysis. Finally report that includes tests/testbenches should be included based on requirements in

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    I'm looking for a developer to create a system for my Zybo Z7 board that can detect people in real-time through a connected pcam5c camera and display the detection text on the video feed...Video Streaming: The video feed should be streamed in real-time. - Text Overlay: The detection results should be displayed as a text overlay on the video. Skills/Experience Required: - Proficient in Xilinx SDK and Xilinx Vivado. - Strong background in object detection, particularly with people. - Previous experience with video processing and streaming. - Knowledge of FPGA programming and VHDL/Verilog is a plus. Please note that my budget for this project is $60. I'm open to hearing from freelancers who can deliver within this budget. I have worked on single pixel (multipixel z...

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    Project VHDL S-a încheiat left

    Hi ExpertSoul, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    I am looking to integrate two ultrasonic sensors onto a Nexys A7 FPGA board using VHDL. My primary goal is using these sensors for object tracking and distance measurement. Integrate TWO HCSR-04 ultrasonic sensors to an Nexys A7 fpga board so that I can read data from both sensors. I need for the seven-segment display that is on the board to show the distances measured. Using a pushbutton on the board, have the display change to show readings from sensor 1 and when pushed the display shows readings from sensor 2 and vice versa. So basically, the pushbutton toggles which sensor's measurement is displayed on the seven segment display. Also, another push button will be used to toggle back and forth between displaying the distance in centimeters (cm) or inches (in) for both sensor...

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    I am looking to integrate two ultrasonic sensors onto a Nexys A7 FPGA board using VHDL. My primary goal is using these sensors for object tracking and distance measurement. Integrate TWO HCSR-04 ultrasonic sensors to an Nexys A7 fpga board so that I can read data from both sensors. I need for the seven-segment display that is on the board to show the distances measured. Using a pushbutton on the board, have the display change to show readings from sensor 1 and when pushed the display shows readings from sensor 2 and vice versa. So basically, the pushbutton toggles which sensor's measurement is displayed on the seven segment display. Also, another push button will be used to toggle back and forth between displaying the distance in centimeters (cm) or inches (in) for both sensor...

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    Urgent
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