Design of high performance signed 2’s complement 4-bit adder circuit using carry Look Ahead Adders

A) Design of high performance signed 2’s complement 4-bit adder circuit using carry Look Ahead Adders. (See [login to view URL] and [login to view URL]) In carry look ahead adders, the carry propagation time is much less than RCA (ripple carry adder). Therefore, the addition process is very fast. As you get more familiar with CLA concept you will understand why we need it for faster adder hardware. Study the ripple carry adder first to appreciate the objectives. You may use transmission gates, static or dynamic CMOS design. 1) Draw a transistor level schematic of the 4-bit CLA in Electric and simulate it in LTSpice. 2) Draw stick diagrams and Euler’s paths where appropriate to design. 3) Perform the Electric Layout with IRSIM. 4) Verify your design by adding the following numbers in signed 2’s complement. All numbers are represented in decimal numbers in the following.: (A) -6+3=-3, (B) -5-1= -6 and (C) 4+2 = 6 to verify. You must provide the 3 additions for verifications. Each verification is worth 3 points. You may provide three cases using one set of waveforms. The figure below is suggested to represented your final answers as an example in one plane of waveforms. 5) Provide details of LTSPICE measurements on rise time, fall time and propagation delays. You can use the measurement feature.