system verilog, uvm
8 freelanceri licitează în medie 44€ pentru acest proiect
I am Electronics Engineers. My Expertise are MATLAB, Simulink, AUTO CAD, Pro E, Verilog, Python, PSSE, PWS, PSS Sincal, ORCAD, Altium(PCB design pursuit) ,MPLAB, Xilinx (VHDL, HDL). PLC, SCADA Systems, Wireshark and pa Mai multe
dear Sir i can do this project. I can assure you that if you work with me once, you will always work with me for these kind of projects.
Hi, Can you share more details about your project? I have done similar project and understood the project outline. Please give me a chance. A trial will convince you. Looking forward to work with you.
I am a qualified design and verification engineer who work on this at industry level. I have more than 4 years+ knowledge in verilog, system verilog and UVM.
I am Currently working on ASIC Verification project in reputed product company, using my skill sets UVM, System Verilog. Previously I had an experience on Verilog for digital design and Verification.
I have about 13 yrs of industry experience in developing verification environment, tests, checkers ..etc in SV and UVM. I would like to pursue your project with professionalism. Let me know what can I do for you. I am Mai multe