Închis

VHDL - Design Programming and Simulation Test Bench

General Information

“Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will

give you additional information about each sub-module of the project in order to realize the counter.

FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!!

Functional Specification

A four-digit counter shall be implemented for the Basys3 FPGA development board. The

FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C).

An asynchronous high-active reset shall be used to initialize the design (BTNC button on the

Basys3 board).

The whole design uses a 100 MHz clock.

One switch for the selection of the count direction (CNT_UP/CNT_DOWN).

‘1’ … count up, ‘0’ … count down.

If the counter reaches the maximum value (minimum value in case of count down) it

continues counting at the minimum value (maximum value in case of count down).

One switch for holding the counter (CNT_HOLD) ‘1’ … hold, ‘0’ … normal operation.

One switch for resetting the counter (CNT_RESET) ‘1’ … reset, ‘0’ … normal operation

The priorities for these switches are:

1. reset

2. hold

3. count direction

The counting mode (decimal, hexadecimal, or octal) and the counting frequency of the least

significant digit (1 Hz, 10 Hz, 100 Hz, or 1000 Hz) depend on your number in the attendance

list as shown in Table 1 (if you work in groups, use the number of the group member with the

lowest number).

All four digits of the counter have to count at the same clock edge, this has to be proven by

simulation.

Aptitudini: Design digital, Electronică, Embedded Systems, FPGA, Verilog / VHDL

Vezi mai multe: vhdl testbench generator, vhdl testbench procedure example, test bench in vhdl pdf, simulation and synthesis in vhdl, vhdl stimulus test bench, vhdl testbench modelsim, vhdl testbench, vhdl testbench for loop

Despre angajator:
( 0 recenzii ) Vienna, Austria

ID Proiect: #18740058

9 freelanceri licitează în medie 44€ pentru acest proiect

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using vhdl and I already have the Basys3 board, please check my profile also please message me so that we can discuss

%bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% EUR în 1 zi
(391 recenzii)
7.8
prakashddit

i have expertise in FPGA since 3+ years. Let's discuss in more detail. life time support will be provided.

%bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% EUR în 1 zi
(7 recenzii)
3.6
erenss

Hi I am an European freelancer having 5 6 years of experience on fpga design using verilog and vhdl. lets discuss the details. I can deliver it in less then 1 day

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% EUR în 2 zile
(8 recenzii)
3.1
Rogtech

Hi Sir, We Rogtech having 5 years of experience in Verilog and VHDL programming. Your project description matches with our expertise and it is proven in Modelsim Simulation. Looking forward to discuss with you in de Mai multe

%bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% EUR în 1 zi
(2 recenzii)
1.5
aeansari80

I'm expert in Mixed signal design with FPGA. I have more than 10 experience in digital processing borads design and implementation. both hardware and software.

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% EUR în 2 zile
(0 recenzii)
0.0
asicdsm

Very similar of a homework done by my students. We also use Basys 3 board. The work will be well done but you will not learn anything.

%bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% EUR în 1 zi
(0 recenzii)
0.0
abehin98en1992

I'm an experienced FPGA design engineer. I'm interested and willing to work with you. Let's discuss more

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% EUR în 2 zile
(0 recenzii)
0.0
techbuzz128

Hi , I am [login to view URL] Design Engineer with 6years experience. I have good experience in vivado as well as on 7 series FPGA boards. You will get 100% Quality and genuine work as per your expectations.

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% EUR în 4 zile
(0 recenzii)
0.0
aleafinclouds

I have done similar project in the past. It seems like a course project and it is quite simple actually.

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% EUR în 2 zile
(0 recenzii)
0.0