PCle, ethernet , UVM, System Verilog
3 freelanceri licitează în medie 170$ pentru acest proiect
I have 10 years of experience in design and verification using Verilog and SystemVerilog, VMM. Please message me. Best regards.
Hello Dear Concern, We are a team of professional members of Electrical, Electronics, Mechanical, Civil, Chemical, Energy, Industrial Engineering. We are also expert in following softwares: MATLAB, Simulink, VHDL, PAD Mai multe
Design/Verification Engineer with experience in large scale complex ICs development/Verification with practicing in Verilog, SystemVerilog, UVM and Programming Python with DUTs Verification. Let's Discuss further.