1. The encoder should include intra mode and inter mode
2. The encoder can encode I frame and P frame.
3. CAVLC is used for entropy encode
4. RDO mode should be implemented and can be chosen based on needs
5. The encoder should have a design to compute the PSNR of YUV components.
6. The code should have notes to help me understand your design.
7. The project should be simulated and synthesized in QuartusII or Xilinx.
8. You should write a document to describe the target and design principle of each module and the relation between different modules.
9. The input of the encoder is a video with QCIF resolution.
10. The output is .264 bits stream. This stream can be decoded correctly with ffmpeg.
11. The last but most important, the encoder should be implemented in Verilog.
10 freelanceri licitează în medie 1001$ pentru acest proiect
Hello ! We want to discuss about your project as we have experience in it. What Differentiates us from the other freelancers : # Experience of more than 5 years in Unity 3D, Xcode, CoCoa 2d, Phonegap and major Mai multe
Dear sir, I have experience with video codecs and FPGA both, I use xilinix and spartan 6 & cyclone -4 boards for development.
Hello, I like to discuss your requirements in brief and present you my queries on your requirements About me: I have 5+years of experience in php WEB APPLICATION and WEBSITE designing and development Technical Sk Mai multe
We have 12 Years Experienced in PHP, HTML, CSS, MySQL, Wordpress, Apache, Server .Net ( C# and Vb.Net ) Android & IOS etc am really good at fixing errors and bugs. I always think outside the box to provide the best Mai multe
Hello, This is not copy/paste message. I read your requirements. I am interested for this job. I have expertise in Wordpress, Laravel, Magento, AngularJS, Ruby on Rails, Core PHP etc. technologies and can work on Mai multe
Please visit my website to see my experience on this field: [login to view URL] Please contact me if we can deal. Thanks
Hello, We are a team of embedded hardware and software professionals with experience in verilog? VHDL and xilinx implementations Would like to know more details about the project. Looking forward to work on thi Mai multe