ASIC IP RTL/TB Development - Looking for Engineers

Închis Postat la acum 3 ani S-au achitat serviciile după ce au fost prestate
Închis S-au achitat serviciile după ce au fost prestate

Job Description :-

We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.

The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.

Job Requirements :-

1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.

2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl [login to view URL] coding will be Perl mixed Verilog/SV.

3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.

4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.

5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.

Who can Apply :-

1) Fresher/junior engineers looking for an opportunity.

2) People looking for training/upscaling in the domain can apply.

3) People looking to explore in-depth from scratch ASIC design can also apply.

Benefits :-

1) Opportunity to work in complex ASIC product design from scratch.

2) Opportunity to learn alongside experienced and passionate engineers.

3) Monthly Stipend/Remuneration.

4) Facility to work remotely.

How To Apply :-

Please apply answering below points -

1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.

2) Which area between design/verification you are more interested in.

Placeholder budget/timeline. Details to be discussed.

If you are sending a proposal, please be available in chat so that details can be discussed.

Verilog / VHDL ASIC Digital ASIC Coding Very-large-scale integration (VLSI) FPGA Network Engineering

ID Proiect: #28680550

Detalii despre proiect

12 propuneri Proiect la distanță Activ acum 3 ani

12 freelanceri plasează o ofertă medie de 464$ pentru proiect


I have 3 years of professional experience working in the field of verification and TB development. I am well versed in all stages of the VLSI work flow. Within 2 years of joining as a fresher in SanDisk India I was the Mai multe

$500 USD în 20 zile
(0 recenzii)

I'm working as Junior RTL engineer so this would be an exciting opportunity for me to explore and deliver the task on time. My skill rating is as below Perl - beginner Verilog - Intermediate SV - begineer

$278 USD în 20 zile
(0 recenzii)

Hey, I am Abdul Rauf, working as a design engineer for two years now, I have expertise in the field of design verification. I have worked with many HDL languages like Verilog and system Verilog. I have also expertise i Mai multe

$500 USD în 7 zile
(0 recenzii)

Hi, I am a trained VLSI Engineer form CDAC good at RTL designing. I have good hands on experience in Verilog HDL and good knowledge in System Verilog and Perl Scripting. My level of expertise in Verilog is Intermedia Mai multe

$500 USD în 7 zile
(0 recenzii)

I am working in Digital Design from last 3 years and my area of Expertise are UVM based Verification plus RTL designing using VeriLog/VhDL/System VeriLog HDL. I have also a little bit experience with Makefile as well Mai multe

$556 USD în 15 zile
(0 recenzii)

I want good project to get experience as I am fresher in this field. But I have 7 years of teaching experience in Electronics domain. I have good knowledge on Digital Electronics, Verilog , Microprocessor. Your one ch Mai multe

$350 USD în 20 zile
(0 recenzii)

Hi there, I am an Associate Design Engineer. I have experiance in IP development and have worked with HDL languages like System Verilog and Verilog. I can write good synthesizable RTL. Also, I am very interested in AS Mai multe

$500 USD în 7 zile
(0 recenzii)

Hi Shivshad, For some reason my account get closed and i am unable to send you message in our conversation chat box. Please create a new thread so we can discuss further. I don't have any contact of you so i am unabl Mai multe

$350 USD în 15 zile
(0 recenzii)