ASIC IP RTL/TB Development - Looking for Engineers -- 2
Buget ₹75000-150000 INR
Job Description :-
We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.
The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.
Job Requirements :-
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl [login to view URL] coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
Benefits :-
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
How To Apply :-
Please apply answering below points -
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.
2) Which area between design/verification you are more interested in.
Placeholder budget/timeline. Details to be discussed.
If you are sending a proposal, please be available in chat so that details can be discussed.
6 freelanceri licitează în medie 110833₹ pentru acest proiect
Hello, I am a digital design engineer with experience (Intermediate + ) in /Verilog/System Verilog. In addition, I have good experience in scripting languages, mainly TCL (intermediate) and Python(expert). I have been Mai multe
Hi , i am working as design and verification engineer. I did MS in embedded systems from LUMS, one of the finest school in pakistan. I have presented two research article. I have follwoing skills: Skills : Verilog, V Mai multe
hello i am an European freelancer having 5 years of experience on fpgas using VHDL and verilog. i donteknow perl.i am expert on verilog and VHDL. and beginner level in sv. i am design engineer having hard experience on Mai multe
I have 3 years of professional experience working in the field of verification and TB development. I am well versed in all stages of the VLSI work flow. Within 2 years of joining as a fresher in SanDisk India I was the Mai multe
Dear Sir/Madam I have 3+years of experience in Software development and Hardware Design. I have completed more than 10 industrial projects. My skills are:- Programming- MATLAB, LabVIEW, Python, FPGA,Verilog and C/C++ Mai multe
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert. perl: Intermediate Verilog: Expert System Verilog: Intermediate 2) Which area between design/verification you are more interest Mai multe
