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9-bit CPU: Register file, ALU, and fetch unit

$30-250 USD

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Data postării: peste 4 ani în urmă

$30-250 USD

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In this lab assignment, you will design the top level, register file, control decoder, ALU (arithmetic logic unit), data memory, muxes (signal routing switches), lookup tables, and fetch unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want the highest level of your design to be a schematic and [System]Verilog code... if you are intersted in let me know . There is instruction that I will shrae with you.
ID-ul proiectului: 21938846

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8 propuneri
Proiect la distanță
Activ: 4 ani în urmă

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Avatarul utilizatorului
Hello! Please check my reviews and profile to know more about me and my work. I’ve helped many students in completing there computer architecture courses and should be able to help you out as well. Please do contact to discuss further! Thank you!
$100 USD în 7 zile
4,9 (82 recenzii)
6,2
6,2
8 freelanceri plasează o ofertă medie de $150 USD pentru proiect
Avatarul utilizatorului
Dear sir I have more than 10 years experience in digital design using verilog and system verilog please check my profile also please message me so that we can discuss
$111 USD în 1 zi
4,9 (448 recenzii)
7,9
7,9
Avatarul utilizatorului
Hi, i am electrical engineer, i can design the ALU using verilog HDL,....................................
$150 USD în 3 zile
4,8 (270 recenzii)
7,2
7,2
Avatarul utilizatorului
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done with very high difficult project in backend design in FPGA by correct timinig closure for FPGA with 400 Mhz in Virtex Ultrascale+ in some field like mining coin (bitcore, and lyra2rev3) Second, with your requirements, I have finished atlest 10 projects related to CPU with ALU, decoder, Datamemory, instruction memory...All of them run very smooth. Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
$200 USD în 3 zile
4,9 (89 recenzii)
6,4
6,4
Avatarul utilizatorului
I have well experienced in doing such kind of jobs.......................................................................................................
$50 USD în 3 zile
4,9 (47 recenzii)
5,7
5,7
Avatarul utilizatorului
Hi I have been working on verilog-vhdl and xilinx and altera(intel) FPGAs by more than 6 year. lets discuss the requirements, the price mentioned is negotiable according to your exact requirements. Thanks
$250 USD în 7 zile
5,0 (30 recenzii)
5,5
5,5
Avatarul utilizatorului
I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.
$88 USD în 3 zile
5,0 (8 recenzii)
4,2
4,2
Avatarul utilizatorului
Hello, I am interested in your IDEA, Can we share with our idea each other? I think you have some mistakes now, thank you!!!
$250 USD în 3 zile
4,7 (4 recenzii)
3,0
3,0

Despre client

Steagul UNITED STATES
La Jolla, United States
5,0
1
Membru din dec. 1, 2016

Verificarea clientului

Mulțumim! Ți-am trimis prin e-mail linkul pe care trebuie să-l accesezi pentru a revendica creditul gratuit.
A apărut o eroare la trimiterea e-mailului. Încearcă din nou.
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