8-BIT NON-PIPELINED PROCESSOR USING VERILOG

Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input can be a sequence of instructions and the final output after executing the entire sequence can be verified. Other than these components, there might be other modules needed depending on your design. You can refer to the construction and working of the MIPS datapath and control path found in the text book “Computer Organization and Design – The Hardware/Software Interface” by Patterson and Hennessy, 5th ed. Also refer to the lecture slides on single cycle non-pipelined processor. Chapter 4 in the above mentioned text book talks about building a datapath and a control path. The instructions that you are required to implement are: i. add ii. addi iii. sub iv. lw v. sw vi. jmp Instruction Opcode add 000 addi 001 sub 010 lw 011 sw 100 jmp 101 The complete RTL schematic of the processor including the datapath and the control path is designed in verilog using the Vivado design suite. After the final design is synthesized, the processor can be simulated to view the inputs and outputs. A bitstream which describes the RTL schematic can be generated from the Vivado project, to test the design on an FPGA board. The FPGA board can be programmed using the bitstream generated from the Vivado design suite. Inputs can be given through push buttons and slide switches and outputs can be represented by LEDs already provided on the board.