debuging existed code in verilog
9 freelanceri licitează în medie 122$ pentru acest proiect
Hey! Please check my profile and reviews to know more about me and my work. It would be great if I could help you out.
I am an electrical engineer with a good experience in Verilog/vhdl and FPGA Projects done (UART and AES) currently working on RISCV
Hi Dear, Hope you doing well! I have read your project details and you are looking for a developer to develop for debugging existed code in Verilog. I am well-versed with my skills. I can start from now. I am a ful Mai multe
Hi there, I am Ahmed an electrical engineer from algeria, i have a good backgound in digital system design using FPGA (verilog and vhdl), i will do quality work and no payment till 100% satisfaction. contact me over ch Mai multe
Hello, I am a PhD scholar in Electronics and Communications Engineering and I received my master in Embedded Systems. I think I can help you. Please provide me more details
have well knowledge of digital electronics and advanced digital system and FPGA circuits. good knowledge in VHDL, Verilog HDL and System Verilog coding both RTL Verification. and FPGA validation with hardware like ALTE Mai multe
Hi Sir, Please share your problems, depend on your design (input/output) we can debug by simulation Or by run on real hardware (using ila core or signal tab to debug) Thanks. Quang
Hi please describe your work. We will need details of your work. We can work together very well. Please text me.