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Verilog Alarm Clock

Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time –this can be adjusted somewhat for simulation purposes).

a) Use multiple input signals (alarm set input, the snooze, and the alarm time).

b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”.

c) An input will be used to set the alarm off.

d) When the simulation starts, a counting mechanism will start counting (representing/roughly simulating a clock).

e) If the alarm set input signal is high, then the alarm should turn on when the count equals the preset alarm value. If at any point during the simulation the alarm set input is switched off, the alarm should turn off by the next complete clock cycle.

f) If the snooze button is activated (assume that snooze is a pulse that is at least one full clock cycle in duration) the alarm should turn off and then turn back on after 5 minutes.

g) Repeat snooze button simulations (pulses) should cause the same behavior in the circuit.

h) If at any time the alarm set input signal goes low, the Alarm_On output should go low by the end of the next complete clock cycle.

i) Clearly describe any additional rules or assumptions.

Write a Verilog code that implements the above alarm clock. Use one-hot encoding for state encoding. Verify the functionality and behavior of the circuit. Use Quartus II toolset. Submit a report containing the following:

1. A state diagram showing the implementation of your design (overview of your design, a detailed description of your approach and design process). Clearly show all the states and the conditions on which transitions occur.

2. Code (Verilog).

3. Annotated (properly labeled) waveforms that demonstrate all the required behavior.

4. RTL schematic of the design after compilation.

5. Roughly, draw the implied hardware of your code. Provide a brief comparison between the tool's RTL schematic and the implied hardware you drew.

6. Extract the highest clock frequency of your design from the compilation report.

Write a Verilog code that implements the above alarm clock. Use one-hot encoding for state encoding. Verify the functionality and behavior of the circuit. Use Quartus II toolset. Submit a report containing the following:

1. A state diagram showing the implementation of your design (overview of your design, a detailed description of your approach and design process). Clearly show all the states and the conditions on which transitions occur.

2. Code (Verilog).

3. Annotated (properly labeled) waveforms that demonstrate all the required behavior.

4. RTL schematic of the design after compilation.

5. Roughly, draw the implied hardware of your code. Provide a brief comparison between the tool's RTL schematic and the implied hardware you drew.

6. Extract the highest clock frequency of your design from the compilation report.

Aptitudini: Verilog / VHDL

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( 0 recenzii ) Stamford, United States

ID Proiect: #29877965

8 freelanceri licitează în medie 71$ pentru acest proiect

(443 recenzii)
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Lightcanon

Hello, I am digital design engineer with +5 years of experience in Verilog RTL coding. I have read your requirements and I know how to properly design the state machine of Alarm clock. So, I am the best to help you. M Mai multe

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sohailnagra

Hi, i have working code of digital alarm in verilog tested in Nexys4 FPGA Board. I can help you in this design. I have more the three and half years of experience in design and verification field. Feel free to ask rega Mai multe

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vinendra77

Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working e Mai multe

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mahan20120

hi , i haved worked verilog about 3 monthes and i think i can help you in , for test my skill and discuss about your project massage me , i will do it in avg 3 days and programming in modelsim

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Engrusman877

Hi, looking for verilog expert. i am an embedded developer. I have 5 years experience in verilog/vhdl. just msg me so we can start working. Thanks

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Kmohansan

Hi, Your project is interesting and good. I am an RTL Design Engineer with 1+ year experience. I can help you on this project. Feel free to ping me for more details.

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bendingreality84

Hi, I have 10+ exp in Verilog & VHDL coding. I have clearly understood your requirement details & ensure that I can complete it on time. Please give me a chance to earn your trust. Looking forward to work with you! Mai multe

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