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verilooger

The aim of this project is to design and implement a digital circuit that enables to find the

minterms of a given Karnaugh map. You should design the circuit by using Verilog and

implement on the FPGA boards in the laboratory. You will be given the truth table and you

will give the information on the truth table as inputs to the system. Your circuit will determine

minterms of the system as sum of products or product of sums. There will be another control

on your circuit that will determine the type of function. You will also implement the same

problem by using NAND gates only and give the function. The circuit will give outputs and

you will use seven segment displays on the Xilinx FPGA board to represent the outputs. Your

outputs on the screen will be the letters that represent the inputs.

Aptitudini: Verilog / VHDL

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Despre angajator:
( 0 recenzii ) Ankara, Turkey

ID Proiect: #4600875

2 freelanceri licitează în medie 708$ pentru acest proiect

amibio

14+ years experience in VHDL/Verilog development. This seems like an interesting project; a little bit vague in its description (what is displayed in the 7-segs; inputs, outputs or both?)

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% USD în 5 zile
(1 părere)
3.7
khanhln

It sound interesting. I'm an expert in Verilog/VHDL as well as algorithm optimization for hardware implementation. Please check PMB

%bids___i_sum_sub_35%%project_currencyDetails_sign_sub_36% USD în 15 zile
(0 recenzii)
0.0