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Circuit Design Electrical Engineering Verilog / VHDL
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Areeb A.

@areebali

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Mixed Signal ASIC Design Engineer

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Canada (10:50 PM)

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Joined on May 1, 2011

My name is Areeb Ali ([login to view URL] graduate, University of Waterloo). My interests include analog/digital circuit and multi-layered custom PCB design. I have wide experience of circuit design and testing on various professional tools like Cadence, Mentor Graphics Pads etc. I designed and taped-out a CMOS Impedance Sensor chip during master’s thesis. I also designed a 4-layer mixed signal PCB, developed test codes on Xilinx and Visual Studio, and successfully carried out the chip testing at Levine Research Labs at University of Waterloo. Currently I am looking for an entry level position in Canada. • The chip is fabricated in a standard mixed-signal 1.8 V 0.18 μm CMOS process. • The sensor data is processed by the on-board Xilinx Spartan 6.0 FPGA, which generates the required digital signals and transmits the impedance information to PC via USB 2.0.

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Experience

Research Assistant

Jul, 2010 - Aug, 2011

•

1 year, 1 month

NUST

Jul, 2010 - Aug, 2011

•

1 year, 1 month

Research Assistant (July 2010-August 2011) NUST-SEECS, Islamabad, Pakistan Work on "Switch Mode Transmitter Architecture" project with hands-on experience in Cadence. Research area includes design and simulation of 4-bit High Speed Flash ADCs (1GHz) based on MCML- 250nm Technology (Delta Sigma Modulators) *Layout Designer of the chip fabricated by IHP Microelectronics, Germany (July, 2011) *Project collaboration with IHP Microelectronics Germany *http://amsg.seecs.

Jul, 2010 - Aug, 2011

•

1 year, 1 month

Education

M.Eng Electrical Engineering

2011 - 2012

•

1 year

2011 - 2012

•

1 year

National University of Science and Technology

2006 - 2010

•

4 years

BE-Electronics Engineering

2006 - 2010

•

4 years

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