Simple FPGA + Quad DAC (3484) Signal Generate

Simple FPGA Signal Generation Using Vivado and LabVIEW on the VC707

The selected engineer must be very fluent in English and have excellent communication skills. The selected engineer must already have and be fluent in the specified Xilinx development tools and software.

The ideal candidate will have both the VC707 and the TI DAC3484EVM or DAC34H84EVM and TI’s FMC to DAC adapter that can work with the VC707 and TI’s DAC EVM. If not, the entire test setup can be accessed via a provided VPN connection. The selected candidate must have signal synthesis experience using high-speed DACs.

The development platform consists of the following elements:

1. A PC with the development and control environment installed

a. Vivado

b. LabVIEW

c. Other development software as needed

2. The Xilinx VC707 development kit

3. TI’s Quad DAC EVM, the DAC3484EVM or equivalent

This simple project includes generation of a single SAWTOOTH waveform obtained by operation of the DAC and observable at this end. The project is to initialize and control the Virtex and DAC on the VC707 through Vivado and LabVIEW. It will need to be demonstrated at our end with a VPN connection that I will provide. The designer can work remotely on the development computer here as required.

The controls will be:

1. INITIALIZE Virtex and DAC

2. START/STOP

3. FREQUENCY

4. AMPLITUDE

We have the latest versions of Vivado and LabVIEW. There is also an interface to the DAC3484 via USB and it is also current. This is a very simple job to start with. It will be followed later in added projects based on what is done here.

Future projects will follow adding on to the basic code developed including:

1. Multiple waveforms

2. Adding controls

3. External Trigger

4. Combining waveforms

5. Etc.

Please see the attached NDA

THE MAXIMUM ACCEPTABLE BID ON THIS PROJECT IS $500. ANY AMOUNT OVER IS DISQUALIFIED. THIS IS A VERY SIMPLE PROJECT TO THE ENGINEER EXPERIENCED IN VIRTEX, VIVADO AND HIGH SPEED DACS.

FPGA Verilog / VHDL

ID Proiect: #6870355

Detalii despre proiect