Verilog Task on Nexys 4 board

Dear sir I have more than 10 years experience in digital design using FPGA please check my profile

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other FPGA projects

I have expertise in Verilog since 3.5+ years.

1.0 year of experience in Analog layout design 3.0 years of experience in FPGA and Embedded System Familiar with device driver development with many interfaces (I2C, UART, SPI, AXI protocol), extensive knowledge about FIFO, Xilinx IP, SDRAM, DDR3, DDR4, Ethernet protocol Experienced in system integration, timing constraints resolution & timing analysis Familiar with Verilog HDL, VHDL, SystemVerilog, C, TCL, Perl Experienced in using EDA tools including: Modelsim, Quartus, Xilinx Vivado, ISE, XPS, SDK, LEDA, VCS, Design Compiler, Prime Time, IC Compiler