Encoding ,modulation/digital modelling

For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail.

Hello, I am an electronics and telecommunication engineer and my major is wireless sytsems' systems' design. I have a solid background in telecommunication theory. I have checked your requirements and I am sure that I can help you with your project. Just let me know and I will do my best to help you. Best regards

Hello, I hope this finds you well. I have just seen your project requiring; Verilog / VHDL Telecommunications Engineering Circuit Design Simulation Analog / Mixed Signal / Digital I believe that my 10-year experience in this field is what you need right away. Avoid the headache of looking further. Let's save time and focus on the real task. My proposed timelines and budget are just placeholder and an open for negotiation to increase or decrease as per the full requirements at hand. Allow me to prove how better my review can be. Smile all the way! Click the message button, so initiate the conversation. Regards, Fridah

Hi I have the experience about the project of introduction of clock jitter in Tx and it is recovered in Rx. In Verilog modeling, PLL, DLL and Manchester encoding/decoding were created and verified. This project is about that "I am Tx and you are Rx and we are communicating wirelessly using Manchester coding scheme, on your side; Rx, you need to have DLL to match with my data_out so you have many delay line stages, one of your stages should match with the rising edge of the clock_out in the mode. That is it. So on my model the DLL stages don't look ok it needs some modifying because I added jitter to the Tx clock, so we need to add filter to this model.I have a low pass filter that I developed from PLL but I don't know how to relate this to DLL" If you need the more details about this project, initiate the chat please Thank you

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution Encoder, Puncture, Interleaver, Modulator, FIR Filter, Demodulator, Deinterleaver, Depuncture and Viterbi Decoder. Previously i was done a project with verilog and the client from Russia to make CRC with 1 bit error correction based on the algorithm that the client gave to me and i have done it <24/7. The other one is i used to solve or do debugging inside the verilog code why the waveform is not equal as expectation. Hopefully my skill and experienced could fulfill this project's requirements. Thank You

Hello, I am an electronics and telecommunication engineer and my major is wireless sytsems' systems' design. I have a solid background in telecommunication theory.