Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and Finite state machines (FSM) and dumped them to Xilinx FPGAs and recently designed a MIPS CPU in Vivado. This is going to be my tenth project in freelancer and i promise to help you in the best as per your need in less time.
You can refer to my portfolio item "verilog codes" and "VHDL codes" at https://www.freelancer.com/u/vinendra77
Thank you