VHDL code for high speed hardware deserializer for DCF/MSF signal

A proposal has not yet been provided

A proposal has not yet been provided

Hey tightass, I know you want my cock. Yes, yes you do want my cock. I have the full design stack up ya ass. If you are Marc, then go fuck yourself bitch.

We are experts in VLSI design and verification. We will deliver design, verification environment and implementation in FPGA for the concept

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience in digital design and well acquainted with ISE, NCverilog, Vivado 2013.4, Altera Quartus 13.0sp1, EDK embedded tools & worked on Virtex-6 ML605, Virtex-5 LX110T, Virtex-4 ML401 , Spartan6, Spartan 3E, SOC Znyq Zedboard and MicroZed boards. I have completed 1G data traffic project where in-depth IEEE Ethernet 802.3 packet parsing is done according to rule set defined for voice & data packets. Each TCP, UDP and SIP packet is processing and transmits to destination and vice versa at receiving end. Xilinx Ethernet core is used only for capturing of packet from FPGA. The clock frequency here is 125Mhz for each sample. I have also completed 10G data traffic project where software part is implemented using Microblaze to configure NELOGIC chip via MDIO protocol & send real time results of 200 registers to PC via uart protocol. The custom IP written in mixed Vhdl / verilog used to handle 10G data Traffic. I have also acquired Xilinx trainings such as Advanced Features & Techniques of Embedded Systems Development, Debugging Tecniques Using ChipScope Pro Tools from So-Logic Vienna. The clock frequency here is 156.25 Mhz for each sample. Please share the project detail. I am free can start work immediately and can work upto 40 hrs per week. Further we can discuss it and I look forward to receiving your response. Regard Mahar

My qualification is M.Tech. in VLSI and Embedded System. I have completed Projects on equalizer, mobile text entry system and dc/dc buck converter using VHDL. I also possess proficiency in various areas like Microcontroller and Verilog / VHDL. I am ready to start working on your job.

I already went through the DCF and MSF signals and 80% of it is coded in VHDL, apart from, this I am very experienced in VHDL, VERILOG programming. I can give you results easily and fast enough

Does this only involves implementing FW? On which platform? What are the DCF and MSF inputs? I would like to get more details on what exactly the project involves.

A proposal has not yet been provided

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